1. Field of the Invention
The present invention relates to the manufacture of high performance VLSI semiconductor chips in general and, more particularly, to a method for producing coplanar metal/insulator films on a substrate according to a chemical-mechanical (chem-mech) polishing technique with an improved polishing slurry. The above method may find extensive use in the fabrication of planarized multilevel metal semiconductor structures.
2. Description of the Prior Art
A semiconductor chip consists of an array of devices whose contacts are interconnected by patterns of wiring metal stripes. In VLSI chips, these metal patterns are multilayered and separated by layers of an insulating material. Interconnections between different metal wiring patterns are made by holes (or via holes), which are etched through said layers of insulating material. Typical chip designs consist of one or two wiring levels, with three wiring levels being the current state of the art. Circuit cost and performance continue to place demand on the fabrication processes in such a way that adding supplementary wiring levels can be competitive even though additional processing steps are required. However, the technique using via-holes, although widely used today, has multiple limitations and drawbacks in that, as the number of metallization layers increases wiring becomes increasingly difficult, as may be clearly understood from FIG. 1.
The semiconductor structure 10 shown in FIG. 1 is a typical example of said current state of the art technology. It is comprised of a silicon substrate 11 of a predetermined conductivity type having a patterned first insulating layer 12 of silicon dioxide (SiO.sub.2) thereon. The first level of metallization is represented by a metal land 13 which makes an electrical contact through via hole 14 with a region 15 of the substrate. It makes contact, for example as an ohmic contact with the emitter region of a bipolar transistor (not represented).
The second level of metallization represented by metal land 16 makes an electrical contact with metal 13 through via hole 17 of the second insulating layer 18. The structure passivated with a third insulating layer 19. Although the structure depicted in FIG. 1 is not to scale, it gives a good idea of the very irregular surface, far from planar, which results from the standard process.
With such a structure, the known dangers are: first of a potential short at locations A between the first and second levels of metallization, due to the thinning of the insulating layer therebetween, and second the risk of a potential open circuit at locations B, due to the thinning of the metal layer at that location (so called necking effect). Those risks are unacceptable for the high standard of reliability which are required in the industry. Therefore, there is a present and serious need to improve the via-hole technique to solve the acute problem of planarizing such irregular surfaces.
A typical example of advanced planarization techniques can be found in European Patent Application No. 80302457.9 to K. Tokitomo et al. According to the teachings of that particular reference, any kind of protuberances at the surface of a semiconductor structure may be removed by the following process: formation of a photoresist layer onto said surfaces, photoresist having a substantially planar surface, and then dry etching the top surface of the structure using a reaction gas which etches both the photoresist and the material forming said protuberances at the same rate. When the material to be removed is phosphosilicate glass (PSG), the reaction gas is a mixture of a fluorine compound and oxygen, when the material is aluminum the reaction gas is a mixture of a chlorine based compound and hydrogen or oxygen. For each material, the reaction gas must be selected appropriately.
This process has several and significant disadvantages which are listed below:
1. Only the second level of metallization (and the following) are planarized, so there still remains a potential risk of necking for the second level metal land (see FIG. 5 of European Patent Application No. 80302457.9).
2. The second insulating layer is very thin at the locations where the first level metal land overlies the first insulating layer. This may cause shorts between metal lines at different levels and undesired parasitic capacitances and coupling as well (see FIG. 5 of European Patent Application No. 80302457.9).
3. The etch back operation must be controlled very accurately, because there is no natural etch stop barrier to end the process, and variations in etch rate exist within a wafer and from wafer to wafer. The risk is to expose the top of the first level metallization (see FIG. 5 of European Patent Application No. 80302457.9).
4. Due to the absence of said etch stop barrier, the dry etching of aluminum is effected in a two step process with a change in the nature of the reaction gas (see FIGS. 12-13).
More generally, plasma etching or Reactive Ion Etching (RIE) of metals with a resist planarizing medium, which appears to be the preferred methods for planarizing semiconductor devices, have limitations inherent to those techniques. First, these techniques cannot be used with all metals but only with those forming volatile reaction products. Then, as far as aluminum is concerned the process is complicated by the presence of a thin Al.sub.2 O.sub.3 layer at the surface of the metal. It has been reported that an unpredictable initiation period is required to remove this Al.sub.2 O.sub.3 layer, followed by a rapid, nonuniform removal of the aluminum layer itself, making this a difficult process to control. Lastly, RIE processes are complex and costly. In addition the use of a resist may also be a source of contamination.
No suggestion is known to have been made so far of using a chem-mech polishing process for planarization of metals and insulators. The use of mechanical polishing (or abrasive polishing) was recently reported in two articles authored by C. H. Scrivner, for the rapid removal of aluminum lands at the second level of metallization for testing purposes.
In the first article, published in the IBM Technical Disclosure Bulletin, Vol. 20, No. 11A, pages 4430-4431, April 1978, the special design of a test site chip is described that lends itself to easy laboratory diagnosis. To use this test site as described one must have the ability to remove the metal at the second level to isolate the via-holes. This is accomplished abrasively by parallel polishing the whole wafer. The metal is left intact in the via-holes for probing purposes. Although the composition of the polishing slurry is not disclosed, a standard polishing slurry such as a water based silica or alumina slurry could be used.
Further information concerning the use of a polishing slurry may be found in the second article published in the IBM Technical Disclosure Bulletin, Vol. 24, No. 4, Sept. 1981, page 2138. According to the latter, the test site chip or a piece of the wafer containing it is mounted on a metal stud (2.5 cm in diameter), which in turn is inserted in a commercial parallel polisher that polishes the surface of the chip. This article clearly points out the disadvantages of the previous cited technique, and in particular it mentions that the polishing step is destructive to the wafer. Also, when only a small area of the wafer is concerned, the article suggests the use of a pencil eraser dipped in a slurry of alumina powder, to manually remove the second level of metal on a limited portion of the chip.
There are a number of reasons that would have prevented one skilled in the art to apply above mechanical polishing techniques with an alumina slurry to the planarization of multilayered metal structures. First, alumina is considered to be an abrasive agent. Although used for lapping, alumina is not used for final chem-mech polishing of silicon substrates due to its higher crystal damage tendency as compared to silica slurries. However, U.S. Pat. No. 4,375,675 to T. Funatsu, describes a polysilicon isolation planarization process using an alumina slurry with alkali additives to give selective chem-mech removal of the polysilicon fill relative to the Si.sub.3 N.sub.4 etch stop layer, but both active and passive devices have not been formed yet at this stage of the process. A similar disclosure may be found in U.S. Pat. No. 3,911,562 to Youmans.
Another reason is that using mechanical polishing with a water based alumina slurry to remove an Al-Cu from an insulating surface does not provide a controllable process for producing metallization structures. Demonstration will be given below (see Table I) that such a slurry polishes Al-Cu and SiO.sub.2 with equal etch rates, leading to significant removal of the insulating layer. So there is still a demand for a new and improved method of producing coplanar metal/insulator films on a substrate.